1. Field of the Invention
The present invention relates to a structure of a dielectric insulation type semiconductor integrated circuit in which a plurality of monocrystalline island regions are integrated with polycrystalline silicon and semiconductor devices are formed in the respective monocrystalline island regions.
2. Description of the Prior Art
One of isolation structures for devices in a semiconductor integrated circuit is a dielectric isolation type structure. In this structure, bottom and side surfaces of a plurality of monocrystalline island regions are coated with dielectric films such as oxide films or the like. The plurality of monocrystalline island regions are integrated so as to bury these surfaces coated with dielectric films in polycrystalline silicon. Devices such as transistors and the like are formed in the respective monocrystalline island regions, and circuit wirings are applied to the devices. Further, as a structure for reducing a collector series resistance of the formed transistor, high impurity concentration regions of the same conductivity type as the respective island regions are provided along the bottom and side surfaces of the respective island regions. These respective monocrystalline island regions are produced in the same step of a process. Therefore, all the high concentration regions are formed so as to have the same thickness in common to the respective monocrystalline island regions.
If a transistor having a high withstand voltage and a transistor having a low withstand voltage are formed in the above-described dielectric isolation type semiconductor integrated circuit in the prior art, a collector series resistance of the transistor having a low withstand voltage would become larger than that of the transistor having a high withstand voltage because a depth of a base region in the former transistor is shallower than that of the latter transistor to prolong the length between the base region and the high concentration region. In order to reduce this collector series resistance of the low withstand voltage transistor, it is necessary to narrow a gap distance between the collector electrode and base region of the transistor or to elongate an opposed length of them. With regard to the gap distance, however, since it is necessary to maintain a withstand voltage of several volts to several tens volts across a base-collector junction even if the transistor is of low withstand voltage class, and so, it is necessary to leave a gap distance of about 10 .about.30 .mu.m. Alternatively, the reduction of the collector series resistance may be achieved by elongating the opposed length of the collector electrode and the base region, but this approach has a shortcoming that an occupation area of the device increases and a parasitic capacitance also becomes large.